The present invention relates to a nonlinear resistor circuit using capacitively-coupled multi-input MOSFETS, and more particularly to a nonlinear negative resistor circuit using capacitively-coupled multi-input MOSFETs.
Devices and circuits having a nonlinear current-voltage (I-V) characteristic, especially those having a negative resistance characteristic, play important roles in logic circuits, memory circuits, oscillators, impedance conversion circuits, various nonlinear signal processing circuits, and chaos generators.
There have been proposed various types of such devices, including a device circuit having a xcex9-type I-V characteristic and realized through combined use of bipolar junction transistors (BJTs) and/or field effect transistors (FETs) (First reference: L. O. Hill, D. O. Pederson, and R. S. Pepper, xe2x80x9cSynthesis of Electronic Bistable Circuits,xe2x80x9d IEEE Transactions on Circuit Theory, vol. CT-10, pp. 25-35, 1963).
Further, a method of effectively realizing the circuit through employment of a technique for integrating two junction FETs (J-FETs) has been proposed (Second reference: G. Kano and H. Iwasa, xe2x80x9cA new A-type Negative Resistance Device of Integrated Complementary FET Structure,xe2x80x9d IEEE Transactions. Electron Devices, vol. 21, no. 7, pp. 448-449, 1974).
Moreover, a xcex9-type transistor circuit that realizes a xcex9-type negative resistance characteristic by use of two MOSFETs has been proposed and applied to an impedance conversion circuit and a neuron circuit (Third reference: Kennosuke Sugisaki, Hisahiro Sekine, Yoshifumi Sekine, Kohei Nakamura, and Masatoshi Suyama, xe2x80x9cA xcex9-type transistor using two MOS-FETs,xe2x80x9d Proc. Denki-Kankei-Gakkai, Tohoku-shibu Rengo-Taikai, 2G9, p. 270, 1978; Fourth reference: Hisahiro Sekine, Kennosuke Sugisaki, Hitoshi Sato, Yoshifumi Sekine, and Masatoshi Suyama, xe2x80x9cThe equivalent inductance using a xcex9-type transistor,xe2x80x9d IEICE Trans., vol. J63-C, no. 5, pp. 325-327, 1980; and Fifth reference: Hoshifumi Sekine, Masahiko Nakamura, Toshiyuki Ochiai, and Masatoshi Suyama, xe2x80x9cUtilization of a xcex9-type transistor for a hardware neuron model,xe2x80x9d IEICE Trans., vol. J68-A, no. 7, pp. 672-679, 1985).
The above-described conventional circuit cannot be integrated by a standard CMOS process in which only enhancement-type MOSFETs are available, because at least one of the MOSFETs in the circuit must be of a depletion type,
An object of the present invention is to provide a nonlinear resistor circuit which utilizes capacitively-coupled multi-input MOSFETs in order to enable integration thereof by a standard CMOS process, and which can realize two types of nonlinear resistance characteristics; i.e., xcex9-type and V-type nonlinear resistance characteristics. Thus, the present invention solves the above-described problems.
The capacitively-coupled multi-input MOSFET comprises a MOSFET and a plurality of capacitors which are connected to the gate terminal in parallel and provide a number of input terminals. The operation of the capacitively-coupled multi-input MOSFET can be controlled through control of voltage applied to one or more of the capacitively-coupled input terminals. The structure of the circuit is the same as a multi-input floating gate MOSFET, which effects a linear weighted summation of input, such as a VMOSFET (see Sixth reference; T. Shibata and T. Ohmi, xe2x80x9cA Functional MOS Transistor Featuring Gate-level Weighted Sum and Threshold Operations,xe2x80x9d IEEE Transactions. Electron Devices, vol. 39, no. 6, pp. 1444-1455, 1992) and an MFMOSFET (see Seventh reference: H. R. Mehrvarz and C. Y. Kwok, xe2x80x9cA Novel Multi-Input Floating-Gate MOS Four-Quadrant Analog Multiplier,xe2x80x9d IEEE J. of Solid State Circuits, vol. 31, no. 8, pp. 1123-1131, 1996).
Since such linear summation does not play an important role in the nonlinear resistor circuit of the present invention, the input coupling capacitors are not required to have linear characteristics. Therefore, as used herein, the term xe2x80x9ccapacitively-coupled multi-input MOSFETxe2x80x9d refers to a more general circuit configuration, including a VMOSFET. Therefore, the nonlinear resistor circuit according to the present invention can be integrated by a less-expensive CMOS process in which linear capacitors are not available.
Further, the size of the nonlinear resistor circuit according to the present invention can be reduced if a floating gate device such as a VMOSFET can be used.
In order to achieve the above object, the present invention provides:
[1] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs, comprising a core circuit which has a nonlinear resistance characteristic and which comprises an enhancement-type first-channel MOSFET having a capacitively-coupled multi-input gate terminal, and an enhancement-type second-channel MOSFET having a capacitively-coupled multi-input gate terminal, the source terminals of the MOSFETs being connected with each other.
[2] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [1] above, wherein the first channel of the core circuit is an N channel, and the second channel of the core circuit is a P channel, so that a xcex9-type current-voltage characteristic is obtained.
[3] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [2] above, wherein the xcex9-type current-voltage characteristic is varied through application of an external control voltage.
[4] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [3] above, wherein, as shown in FIGS. 6(a)-6(p), a fifth potential (vX) is provided between the drain terminal (A) of the N-channel MOSFET and a first input/output terminal (X); a sixth potential (VY) is provided between the drain terminal (B) of the P-channel MOSFET and a second input/output terminal (Y); a first potential (vP1A, vP1X) is provided between the drain terminal (A) of the N-channel MOSFET and a first capacitor (CP1) connected to the gate of the P-channel MOSFET or between the first input/output terminal (X) and the first capacitor (CP1); a second potential (VP2B, VP2Y) is provided between the drain terminal (B) of the P-channel MOSFET and a second capacitor (CP2) connected to the gate of the P-channel MOSFET or between the second input/output terminal (Y) and the second capacitor (CP2); a third potential (vN1B, vN1Y) is provided between the drain terminal (B) of the P-channel MOSFET and a third capacitor (CN1) connected to the gate of the N-channel MOSFET or between the second input/output terminal (Y) and the third capacitor (CN1); and a fourth potential (vN2B, vN2Y) is provided between the drain terminal (B) of the P-channel MOSFET and a fourth capacitor (CN2) connected to the gate of the N-channel MOSFET or between the second input/output terminal (Y) and the fourth capacitor (CN2).
[5] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [1] above, wherein the first channel of the core circuit is a P channel, and the second channel of the core circuit is an N channel, so that a V-type current-voltage characteristic is obtained.
[6] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [5] above, wherein the V-type current-voltage characteristic is varied through application of an external control voltage,
[7] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [6] above, wherein, as shown in FIGS. 8(a)-8(p), an eleventh potential (vX) is provided between the drain terminal (B) of the P-channel MOSFET and a first input/output terminal (X); a twelfth potential (vY) is provided between the drain terminal (A) of the N-channel MOSFET and a second input/output terminal (Y); a seventh potential (vN2A, vN2X) is provided between the drain terminal (B) of the P-channel MOSFET and a fifth capacitor (CN2) connected to the gate of the N-channel MOSFET or between the first input/output terminal (X) and the fifth capacitor (CN2); an eighth potential (vN1A, vN1Y) is provided between the drain terminal (A) of the N-channel MOSFET and a sixth capacitor (CN1) connected to the gate of the N-channel MOSFET or between the second input/output terminal (Y) and the sixth capacitor (CN1); a ninth potential (vP2A, vP2Y) is provided between the drain terminal (A) of the N-channel MOSFET and a seventh capacitor (CP2) connected to the gate of the P-channel MOSFET or between the second input/output terminal (Y) and the seventh capacitor (CP2); and a tenth potential (vP1A, vP1Y) is provided between the drain terminal (A) of the N-channel MOSFET and an eighth capacitor (CP1) connected to the gate of the P-channel MOSFET or between the second input/output terminal (Y) and the eight capacitor (CP1).